1. Field of the Invention
The present invention generally relates to a display panel, and more particularly, to a display panel capable of enhancing protection of a peripheral circuit thereon.
2. Description of Related Art
With advantages of high definition, small volume, light weight, low driving voltage, low power consumption, and a wide range of applications, a liquid crystal display (LCD) has replaced a cathode ray tube (CRT) display and has become the mainstream display product in the next generation. A conventional LCD panel is formed by a color filter substrate having a color filter layer, a thin film transistor (TFT) array substrate, and a liquid crystal layer sandwiched between the color filter substrate and the TFT array substrate.
In general, an active array substrate has an active area and a peripheral circuit area. A plurality of pixels are disposed in the active area to form a pixel array, and a peripheral circuit is formed in the peripheral circuit area. Each of the pixels includes a TFT and a pixel electrode connected thereto. Additionally, each of the pixels is surrounded by two adjacent scan lines and two adjacent data lines. These scan lines and data lines are often extended from the active area to the peripheral circuit area and connected to the aforesaid peripheral circuit, and the peripheral circuit is further connected to an external driver integrated circuit (IC).
FIG. 1A is a schematic view of a conventional display panel. FIG. 1B is a schematic partial top view of outer lead bonding (OLB) areas in a peripheral circuit depicted in FIG. 1A. FIG. 1C is a schematic cross-sectional view taken along a line A-A′ depicted in FIG. 1B. Referring to FIG. 1A, the conventional display panel 100 includes a first substrate 110, a second substrate 120, a display area 112, and a peripheral area 114. The second substrate 120 is disposed on the display area 112 of the first substrate 110. The peripheral area 114 includes a gate OLB area 114a and a source OLB area 114b. 
Next, referring to FIGS. 1B and 1C, a plurality of metal wirings M1 and a plurality of metal wirings M2 are disposed in the gate OLB area 114a of the peripheral area 114, and an insulating layer GI is disposed between the metal wirings M1 and M2. Through pads P of the metal wirings M1, a pixel electrode PE can be electrically connected to a driving circuit (not shown).
Nevertheless, in the conventional display panel 100, the second substrate 120 does not cover the peripheral area 114. In other words, intersections of the metal wirings M1 and the metal wirings M2 on the first substrate 110 are exclusively covered by a protection layer 112. Here, the protection layer 112 is usually constituted by silicon nitride or silicon oxide having a thickness in a micrometer scale, and therefore the protection layer 112 is very much likely to be scratched during fabrication and testing. Specifically, since the metal wirings M1 and the metal wirings M2 transmit different signals, when the intersections of the metal wirings M1 and the metal wirings M2 are scratched, abnormal image signals are generated in the display panel 100. Thereby, yield rate of the display panel 100 is reduced.